ds013 (v1.2) may 3, 2000 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2000 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to change without notice. features ? 7.5 ns pin-to-pin logic delays system frequencies up to 140 mhz 256 macrocells with 6,000 usable gates available in small footprint packages - 144-pin tqfp (116 user i/o pins) - 208-pin pqfp (160 user i/o) - 280-ball cs bga (160 user i/o) optimized for 3.3v systems - ultra low power operation - 5v tolerant i/o pins with 3.3v core supply - advanced 0.35 micron five metal layer re- programmable process - fzp? cmos design technology advanced system features - in-system programming - input registers - predictable timing model - up to 23 clocks available per logic block - excellent pin retention during design changes - full ieee standard 1149.1 boundary-scan (jtag) - four global clocks - eight product term control terms per logic block fast isp programming times port enable pin for additional i/o 2.7v to 3.6v industrial grade voltage range programmable slew rate control per output security bit prevents unauthorized access refer to xpla3 family data sheet (ds012) for architecture description description the xcr3256xl is a 3.3v, 256 macrocell cpld targeted at power sensitive designs that require leading edge program- mable logic solutions. a total of 16 logic blocks provide 6,000 usable gates. pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 mhz. totalcmos? design technique for fast zero power xilinx offers a totalcmos cpld, both in process technol- ogy and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows xilinx to offer cplds that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 1 and ta b l e 1 showing the i cc vs. fre- quency of our xcr3256xl totalcmos cpld (data taken with 16 up/down, loadable 16-bit counters at 3.3v, 25 c). 0 xcr3256xl 256 macrocell cpld ds013 (v1.2) may 3, 2000 014 preliminary product specification r
xcr3256xl 256 macrocell cpld 2 www.xilinx.com ds013 (v1.2) may 3, 2000 1-800-255-7778 preliminary product specification r dc electrical characteristics over recommended operating conditions (1) figure 1: xcr3256xl typical i cc vs. frequency at v cc = 3.3v, 25 c table 1: typical i cc vs. frequency at v cc = 3.3v, 25 c frequency (mhz) 0 1 10 20 40 60 80 100 120 140 ty p i c a l i cc (ma) 0.02 0.91 8.87 17.7 34.8 51.5 68 84.2 100.1 116.6 symbol parameter test conditions min. max. unit v oh output high voltage for 3.3v outputs i oh = ? 8 ma 2.4 - v v ol output low voltage for 3.3v outputs i ol = 8 ma - 0.4 v i il input leakage current v in = gnd or v cc ? 10 10 m a i ih i/o high-z leakage current v in = gnd or v cc ? 10 10 m a i ccsb standby current v cc = 3.6v - 100 m a i cc dynamic current (2,3) f = 1 mhz - 2 ma f = 50 mhz - 60 ma c in input pin capacitance (4) f = 1 mhz - 8 pf c clk clock input capacitance (4) f = 1 mhz 5 12 pf c i/o i/o pin capacitance (4) f = 1 mhz - 10 pf notes: 1. see xpla3 family data sheet (ds012) for recommended operating conditions. 2. see ta b l e 1 , figure1 for typical values. 3. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 4. typical values not tested. 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 160 frequency (mhz) typical icc (ma)
xcr3256xl 256 macrocell cpld ds013 (v1.2) may 3, 2000 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r ac electrical characteristics over recommended operating conditions (1,2) symbol parameter -7 -10 -12 unit min. max. min. max. min. max. t pd1 propagation delay time (single p-term) - 7.0 - 9.0 - 10.8 ns t pd2 propagation delay time (or array) (3) - 7.5 - 10.0 - 12.0 ns t co clock to output (global synchronous pin clock) - 4.5 - 5.8 - 6.9 ns t suf setup time fast 2.0 - 2.5 - 3.0 - ns t su setup time 4.8 - 6.5 - 7.9 - ns t h hold time 0-0-0-ns t wlh global clock pulse width (high or low) 3.0 - 4.0 - 5.0 - ns t plh p-term clock pulse width (high or low) 4.5 - 6.0 - 7.5 - ns t r input rise time - 20 - 20 - 20 ns t l input fall time - 20 - 20 - 20 ns f system maximum system frequency - 140 - 105 - 88 mhz t config configuration time (4) -40-40-40 m s t poe p-term oe to output enabled - 9.0 - 11.0 - 13.0 ns t pod p-term oe to output disabled (5) - 9.0 - 11.0 - 13.0 ns t pco p-term clock to output - 8.0 - 10.3 - 12.4 ns t pao p-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns notes: 1. specifications measured with one output switching. 2. see xpla3 family data sheet (ds012) for recommended operating conditions. 3. see figure 4 for derating. 4. typical current draw during configuration is 10 ma at 3.6v. 5. output c l = 5 pf.
xcr3256xl 256 macrocell cpld 4 www.xilinx.com ds013 (v1.2) may 3, 2000 1-800-255-7778 preliminary product specification r timing model the xpla3 architecture follows a simple timing model that allows deterministic timing in design and redesign. the basic timing model is shown in figure 2 . one key feature of the xpla3 cpld is the ability to have up to 48 product term inputs into a single macrocell and maintain consistent tim- ing. this is achieved through the use of a fully populated pla (programmable and programmable or array) which also has the ability to share product terms and only use the required amount of product terms per macrocell. there is a fast path (t logi1 ) into the macrocell which is used if there is a single product term. the t logi2 path is used for multiple product term timing. for optimization of logic, the xpla3 cpld architecture includes a fold-back nand path (t logi3 ). there is a fast input path to each macrocell if used as an input register (t fin ). xpla3 also includes universal control terms (t uda ) that can be used for synchronization of the macrocell registers in different logic blocks. there is also slew rate control and output enable control on a per macrocell basis. figure 2: xpla3 timing model t in t f t out t en t slew t logi1,2 dlt q ce s/r t logi3 t fin t gck t uda ds017_02_042800
xcr3256xl 256 macrocell cpld ds013 (v1.2) may 3, 2000 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r internal timing parameters symbol parameter -7 -10 -12 unit min. max. min. max. min. max. buffer delays t in input buffer delay - 2.5 - 3.3 - 4.0 ns t fin fast input buffer delay - 2.2 - 2.8 - 3.3 ns t gck global clock buffer delay - 1.0 - 1.3 - 1.5 ns t out output buffer delay - 2.5 - 2.8 - 3.3 ns t en output buffer enable/disable delay - 4.5 - 5.2 - 6.0 ns internal register and combinatorial delays t ldi latch transparent delay - 1.3 - 1.6 - 2.0 ns t sui register setup time 0.8 - 1.0 - 1.2 - ns t hi register hold time 4.0 - 5.5 - 6.7 - ns t ecsu register clock enable setup time 2.0 - 2.5 - 3.0 - ns t echo register clock enable hold time 3.0 - 4.5 - 5.5 - ns t coi register clock to output delay - 1.0 - 1.3 - 1.6 ns t aoi register async. s/r to output delay - 2.0 - 2.0 - 2.2 ns t rai register async. recovery - 5.0 - 7.0 - 8.0 ns t logi1 internal logic delay (single p-term) - 2.0 - 2.5 - 3.0 ns t logi2 internal logic delay (pla or term) - 2.5 - 3.5 - 4.2 ns feedback delays t f zia delay - 2.8 - 3.7 - 4.4 ns time adders t logi3 fold-back nand delay - 6.0 - 8.0 - 9.5 ns t uda universal delay - 2.0 - 2.5 - 3.0 ns t slew slew rate limited delay - 4.0 - 5.0 - 6.0 ns
xcr3256xl 256 macrocell cpld 6 www.xilinx.com ds013 (v1.2) may 3, 2000 1-800-255-7778 preliminary product specification r switching characteristics figure 3: ac load circuit v cc v out v in c1 r1 r2 s1 s2 ds013_03_050200 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t poe (high) t poe (low) t p open closed closed open closed closed note: for t pod , c1 = 5 pf figure 4: derating curve for t pd2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 124816 ds013_04_042800 number of adjacent outputs switching (ns) figure 5: voltage waveform 90% 10% 1.5 ns 1.5 ns ds017_05_042800 +3.0v 0v measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. t r t l
xcr3256xl 256 macrocell cpld ds013 (v1.2) may 3, 2000 www.xilinx.com 7 preliminary product specification 1-800-255-7778 r pin descriptions table 2: xcr3256xl pin descriptions function cs280 pq208 tq144 bscan order a0 e18 6 106 736 a1 e19 7 - 732 a2 f15* 8* 104 (tdo) 728* a3 f17 9 103 724 a4 f1810102720 a11 f19 11 101 710 a12 g16 12 100 706 a13 g17 13 99 702 a14 g19 15 - 698 a15 h16 16 - 694 b0 b19 4 107 552 b1 b18 3 108 548 b2 b17 206 - 544 b3 a18 205 - 540 b4 a17 204 109 536 b11 c16 203 110 526 b12 a16 202 111 522 b13 e15 201 - 518 b14 d15 199 112 514 b15 a15 198 113 510 c0 h17 17 98 690 c1 h18 18 97 686 c2 h19 19 96 682 c3 j16 20 94 678 c4 j17 21 93 674 c11 j18 22 92 664 c12 k16 24 - 660 c13 k17 25 91 656 c14 k18 26 90 652 c15 l16 27 - 648 clk0/in0 a10 181 128 - clk1/in1 d11 182 127 - clk2/in2 c11 183 126 - clk3/in3 b11 184 125 - d0 e14 197 114 506 d1 d14 196 116 502 d2 a14 195 117 498 d3 c13 194 - 494 d4 b13 193 118 490 d11 a13 192 119 480 d12 a12 190 120 476 d13 c12 (tdo) 189 (tdo) 121 - d14 b12 188 - 468 d15 d12 187 122 464 e0 l17* 28* 89 (tck) 644* e1 l18 29 - 640 e2 l19 (tck) 30 (tck) 88 - e3 m16 31 87 632 e4 m18 33 86 628 e11 m17 34 84 618 e12 n16 35 - 614 e13 n19 36 83 610 e14 n18 37 82 606 e15 n17 38 - 602 f0 u10 78 - 460 f1 t10 77 55 456 f2 w11 76 56 452 f3 u11 73 - 448 f4 t11 71 60 444 f11 w12 70 61 434 f12 u12 69 62 430 f13 t12 68 63 426 f14 v13 67 - 422 f15 u13 66 65 418 g0 p16 39 81 598 g1 p18 40 - 594 g2 r19 42 80 590 g3 r16 43 79 586 g4 r18 44 78 582 ta b l e 2 : xcr3256xl pin descriptions (continued) function cs280 pq208 tq144 bscan order *note: bscan order for cs280 and pq208 only.
xcr3256xl 256 macrocell cpld 8 www.xilinx.com ds013 (v1.2) may 3, 2000 1-800-255-7778 preliminary product specification r g11 r17 45 77 572 g12 r15 46 - 568 g13 t17 47 75 564 g14 t16 48 74 560 g15 u19 49 - 556 gnd e10 82 52 - gnd e11 75 57 - gnd e12 185 124 - gnd e13 180 129 - gnd e5 152 3 - gnd e7 134 17 - gnd e8 94 33 - gnd e9 72 59 - gnd g15 50 64 - gnd g5 32 85 - gnd h15 14 105 - gnd h5 200 135 - gnd j15 174 - - gnd j5 - - - gnd k15 - - - gnd k5 - - - gnd l15 - - - gnd l5 - - - gnd m15 - - - gnd m5 - - - gnd n15 - - - gnd n5 - - - gnd r7 - - - gnd r8 - - - gnd r9 - - - gnd r10 - - - gnd r11 - - - gnd r12 - - - gnd r13 - - - h0 t13 65 66 414 h1 w14 64 67 410 table 2: xcr3256xl pin descriptions (continued) function cs280 pq208 tq144 bscan order h2 t14 62 68 406 h3 r14 61 69 402 h4 w15 60 - 398 h11 u15 59 70 388 h12 v15 58 - 384 h13 t15 57 71 380 h14 v16 56 - 376 h15 w17 55 72 372 i0 b1 153 2 368 i1 c3 154 1 364 i2 a4 159 - 360 i3 b5 160 - 356 i4 c5 161 143 352 i11 a5 162 - 342 i12 e6 163 142 338 i13 d6 164 141 334 i14 b6 166 140 330 i15 a6 167 139 326 j0 d2* 151* 4 (tdi) 184* j1 d1 150 - 180 j2 e3 149 5 176 j3 e2 148 6 172 j4 e4 147 7 168 j11 e1 146 8 158 j12 f5 145 - 154 j13 f3 144 9 150 j14 f4 142 10 146 j15 g3 141 11 142 k0 d7 168 - 322 k1 c7 169 - 318 k2 b7 170 138 314 k3 a7 171 - 310 k4 c8 172 137 306 k11 b8 173 136 296 k12 c9 175 134 292 k13 b9 (tdi) 176 (tdi) 133 - ta b l e 2 : xcr3256xl pin descriptions (continued) function cs280 pq208 tq144 bscan order *note: bscan order for cs280 and pq208 only.
xcr3256xl 256 macrocell cpld ds013 (v1.2) may 3, 2000 www.xilinx.com 9 preliminary product specification 1-800-255-7778 r k14 d10 177 132 284 k15 c10 178 131 280 l0 g2 140 - 138 l1 g1 139 - 134 l2 g4 138 12 130 l3 h1 137 14 126 l4 h3 136 15 122 l11 h2 135 16 112 l12 j2 133 - 108 l13 j3 132 18 104 l14 k2 131 19 100 l15 k3 130 - 96 m0 w10 79 - 276 m1 t9 80 54 272 m2 u9 81 53 268 m3 t8 84 - 264 m4 t7 86 49 260 m11 w7 87 48 250 m12 v7 88 47 246 m13 u7 89 46 242 m14 w6 90 - 238 m15 t6 91 45 234 n0 k4* 129* 20 (tms) 92* n1 l1 128 - 88 n2 l2 (tms) 127 (tms) 21 - n3 l3 126 22 80 n4 m1 124 23 76 n11 m3 123 25 66 n12 m4 122 - 62 n13 n1 121 26 58 n14 n2 120 27 54 n15 n3 119 28 50 o0 v6 92 44 230 o1 u6 93 43 226 o2 r6 95 42 222 table 2: xcr3256xl pin descriptions (continued) function cs280 pq208 tq144 bscan order o3 w5 96 41 218 o4 t5 97 40 214 o11 v5 98 - 204 o12 u5 99 39 200 o13 w4 100 38 196 o14 u4 101 - 192 o15 w3 102 37 188 p0 p1 118 - 46 p1 p2 117 - 42 p2 p4 115 29 38 p3 r3 114 30 34 p4 r2 113 31 30 p11 r4 112 32 20 p12 t3 111 - 16 p13 u1 110 34 12 p14 v1 109 35 8 p15 u2 108 36 4 port_en p3 116 13 - v cc v9 83 51 - v cc v11 74 58 - v cc a11 186 123 - v cc b10 179 130 - v cc f2 143 24 - v cc l4 125 50 - v cc v2 107 73 - v cc u8 85 76 - v cc u14 63 95 - v cc t18 41 115 - v cc p15 23 144 - v cc j19 5 - - v cc d17 191 - - v cc c14 165 - - v cc d13 - - - v cc c6 - - - ta b l e 2 : xcr3256xl pin descriptions (continued) function cs280 pq208 tq144 bscan order *note: bscan order for cs280 and pq208 only.
xcr3256xl 256 macrocell cpld 10 www.xilinx.com ds013 (v1.2) may 3, 2000 1-800-255-7778 preliminary product specification r ordering information revision history the following table shows the revision history for this document table 3: xcr3256xl jtag pinout by package type device xcr3256xl (pin number) tck port enable tms tdi tdo 144-pin tq 89 13 20 4 104 208-pin pq 30 116 127 176 189 280-pin cs l19 p3 l2 b9 c12 example: xcr3256xl -7 pq 208 c temperature range number of pins package type speed options -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay temperature range c = commercial, t a = 0 c to +70 c i = industrial, t a = ? 40 c to +85 c packaging options tq144: 144-pin thin quad flat package pq208: 208-pin plastic quad flat package cs280: 280-ball chip scale package device type speed options component compatibility pins 144 208 280 type plastic tqfp plastic pqfp plastic bga code tq144 pq208 cs280 xcr3256xl -7 c c c -10 c, i c, i c, i -12 c, i c, i c, i date version revision 01/21/00 1.0 initial xilinx release. 02/10/00 1.1 updated pinout table. 05/03/00 1.2 minor updates and added boundary scan to pinout table.
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